Guide to RISC Processors

for Programmers and Engineers

By Sivarama P. Dandamudi

Guide to RISC Processors Cover Image

  • ISBN13: 978-0-3872-1017-9
  • 404 Pages
  • User Level: Professionals
  • Publication Date: December 6, 2005
  • Available eBook Formats: PDF
  • eBook Price: $99.00
Buy eBook Buy Print Book Add to Wishlist

Related Titles

Full Description
Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide instruction on MIPS assembly language programming, so that readers can readily learn the concepts and principles introduced earlier. Professionals, programmers, and students in computer architecture and programming courses will find the guide an essential resource.
Table of Contents

Table of Contents

  1. Part I. Overview: Introduction. Processor design issues. RISC principles.
  2. Part II. Architectures: MIPS architecture. SPARC architecture. PowerPC architecture. Itanium architecture. ARM architecture.
  3. Part III. Mips Assembly Language: SPIM simulator and debugger. Assembly language overview. Procedures and the stack. Addressing modes. Arithmetic instructions. Conditional execution. Logical and shift operations. Recursion. Floating
  4. point operations.
  5. Appendixes: Number Systems. Character Representation. MIPS Instruction Set Summary. Programming Exercises.
  6. Bibliography.
  7. Index.
Errata

Please Login to submit errata.

No errata are currently published