Digital System Test and Testable Design

Using HDL Models and Architectures

By Zainalabedin Navabi

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Using Verilog models and test benches for implementing and explaining fault simulation and test generation algorithms, this book treats the concepts of testing and testability in digital systems, and also covers digital design practices and methodologies.

Full Description

  • ISBN13: 978-1-4419-7547-8
  • 452 Pages
  • Publication Date: December 20, 2010
  • Available eBook Formats: PDF
  • eBook Price: $99.00
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Full Description
This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.
Table of Contents

Table of Contents

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