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Intel Xeon Phi Coprocessor Architecture and Tools

The Guide for Application Developers

Authors: Rahman, Rezaur

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  • Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in technical computing applications.

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eBook  
  • ISBN 978-1-4302-5927-5
  • This book is an open access book, you can download it for free on link.springer.com
Softcover $24.99
price for USA
  • ISBN 978-1-4302-5926-8
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor.

Xeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them.

In this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel.

About the authors

Rezaur Rahmanis a Senior Staff Engineer in the Intel Software and Services Group. He played a key role in the inception and development of the Xeon Phi coprocessor for technical computing applications by demonstrating the viability of applying Intel s manycore graphics processor codenamed Larrabee to solving technical computing problems. He led the worldwide technical enabling team for Intel Xeon Phi products, focused on porting and optimizing applications on the Xeon Phi coprocessor for hundreds of technical computing customers. He has worked internally with hardware architects and Intel compiler and tools teams to optimize and add features to improve the performance of Intel Many Integrated Core (MIC) and Xeon Phi software and hardware components. With 25 years experience in computer architecture and software design, Rahman contributes his expertise in technical code optimization, performance tuning, and hardware microarchitectural analysis in the HPC domain to various industry standardization groups such as the World Wide Web Consortium (W3C). Rahman holds a master s degree in computer science from Texas A&M University and a bachelor s in electrical engineering from Bangladesh University of Engineering and Technology.

Table of contents (14 chapters)

  • Introduction to Xeon Phi Architecture

    Rahman, Rezaur

    Pages 3-14

  • Programming Xeon Phi

    Rahman, Rezaur

    Pages 15-30

  • Xeon Phi Vector Architecture and Instruction Set

    Rahman, Rezaur

    Pages 31-48

  • Xeon Phi Core Microarchitecture

    Rahman, Rezaur

    Pages 49-64

  • Xeon Phi Cache and Memory Subsystem

    Rahman, Rezaur

    Pages 65-80

Buy this book

eBook  
  • ISBN 978-1-4302-5927-5
  • This book is an open access book, you can download it for free on link.springer.com
Softcover $24.99
price for USA
  • ISBN 978-1-4302-5926-8
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.

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Bibliographic Information

Bibliographic Information
Book Title
Intel Xeon Phi Coprocessor Architecture and Tools
Book Subtitle
The Guide for Application Developers
Authors
Copyright
2013
Publisher
Apress
Copyright Holder
Rezaur Rahman
eBook ISBN
978-1-4302-5927-5
DOI
10.1007/978-1-4302-5927-5
Softcover ISBN
978-1-4302-5926-8
Edition Number
1
Number of Pages
XXI, 232
Topics