Overview
- Unified theory of register-transfer logic and computer arithmetic
- Comparative analysis of sophisticated hardware solutions
- Verification methodology combining theorem proving with equivalence checking
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About this book
This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations.
As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings.
This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I—III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V.Similar content being viewed by others
Keywords
Table of contents (22 chapters)
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Front Matter
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Part I
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Front Matter
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Part II
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Front Matter
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Part III
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Front Matter
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Part IV
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Front Matter
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Part V
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Front Matter
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Authors and Affiliations
About the author
David M. Russinoff is Senior Principal Engineer at Arm Holdings. He holds a bachelor's degree from the Massachusetts Institute of Technology and a doctorate from New York University, both in mathematics, and a master's in computer sciences from the University of Texas at Austin. He has spent twenty-five years developing mathematical methods of hardware verification, with an emphasis on interactive theorem proving, and applying them in the analysis of commercial designs, especially arithmetic circuits.
Bibliographic Information
Book Title: Formal Verification of Floating-Point Hardware Design
Book Subtitle: A Mathematical Approach
Authors: David M. Russinoff
DOI: https://doi.org/10.1007/978-3-030-87181-9
Publisher: Springer Cham
eBook Packages: Computer Science, Computer Science (R0)
Copyright Information: The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2022
Hardcover ISBN: 978-3-030-87180-2Published: 04 March 2022
Softcover ISBN: 978-3-030-87183-3Published: 05 March 2023
eBook ISBN: 978-3-030-87181-9Published: 03 March 2022
Edition Number: 2
Number of Pages: XXVIII, 436
Number of Illustrations: 40 b/w illustrations
Topics: Arithmetic and Logic Structures, Computer Hardware, Processor Architectures, Circuits and Systems