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Intelligent Memory Systems

Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers

  • Conference proceedings
  • © 2001

Overview

Editors:
  1. Frederic T. Chong

    1. Dept. of Computer Science, University of California, Davis, USA

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  2. Christoforos Kozyrakis

    1. EECS Computer Science Division, University of California, Berkeley, USA

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  3. Mark Oskin

    1. Dept. of Computer Science, University of California, Davis, USA

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2107)

Included in the following conference series:

Conference proceedings info: IMS 2000.

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Table of contents (16 papers)

  1. Front Matter

    Pages I-VIII
    Download chapter PDF

  2. Memory Technology

    1. A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro

      • Junji Ogawa, Mark Horowitz
      Pages 1-14

    2. Software Controlled Reconfigurable On-chip Memory for High Performance Computing

      • Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku
      Pages 15-32

  3. Processor and Memory Architecture

    1. Content-Based Prefetching: Initial Results

      • Robert Cooksey, Dennis Colarelli, Dirk Grunwald
      Pages 33-55

    2. Memory System Support for Dynamic Cache Line Assembly

      • Lixin Zhang, Venkata K. Pingali, Bharat Chandramouli, John B. Carter
      Pages 56-70

    3. Adaptively Mapping Code in an Intelligent Memory Architecture

      • Yan Solihin, Jaejin Lee, Joseph Torrellas
      Pages 71-84

  4. Applications and Operating Systems

    1. The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems⋆

      • Richard C. Murphy, Peter M. Kogge, Arun Rodrigues
      Pages 85-103

    2. Memory Management in a PIM-Based Architecture

      • Mary Hall, Craig Steele
      Pages 104-121

  5. Compiler Technology

    1. Exploiting On-chip Memory Bandwidth in the VIRAM Compiler

      • David Judd, Katherine Yelick, Christoforos Kozyrakis, David Martin, David Patterson
      Pages 122-134

    2. FlexCache: A Framework for Flexible Compiler Generated Data Caching

      • Csaba Andras Moritz, Matthew I. Frank, Saman Amarasinghe
      Pages 135-146

  6. Poster Session

    1. Aggressive Memory-Aware Compilation

      • Peter Grun, Nikil Dutt, Alex Nicolau
      Pages 147-151

    2. Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆

      • Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
      Pages 152-159

    3. SAGE: A New Analysis and Optimization System for FlexRAM Architecture

      • Tsung-Chuan Huang, Slo-Li Chu
      Pages 160-168

    4. Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems

      • Koji Inoue, Koji Kai, Kazuaki Murakami
      Pages 169-178

    5. The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems

      • Jeff La Coss
      Pages 179-182

    6. Compiler-Directed Cache Line Size Adaptivity ⋆

      • Dan Nicolaescu, Xiaomei Ji, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
      Pages 183-187

    7. Summary of Question/Answer Sessions for Workshop Presentations

      Pages 188-191

  7. Back Matter

    Pages 193-193
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About this book

We are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and systems for computation in memory have developed quickly. The focus of this workshop was to bring together researchers from academia and industry to discuss recent progress and future goals. The program committee selected 8 papers and 6 poster session abstracts from 29 submissions for inclusion in the workshop. Four to five members of the program committee reviewed each submission and their reviews were used to numerically rank them and guide the selection process. We believe that the resulting program is of the highest quality and interest possible. The selected papers cover a wide range of research topics such as circuit technology, processor and memory system architecture, compilers, operating systems, and applications. They also present a mix of mature projects, work in progress, and new research ideas. The workshop also included two invited talks. Dr. Subramanian Iyer (IBM Microelectronics) provided an overview of embedded memory technology and its potential. Dr. Mark Snir (IBM Research) presented the Blue Gene, an aggressive supercomputer system based on intelligent memory technology.

Editors and Affiliations

  • Dept. of Computer Science, University of California, Davis, USA

    Frederic T. Chong, Mark Oskin

  • EECS Computer Science Division, University of California, Berkeley, USA

    Christoforos Kozyrakis

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