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SAT-Based Scalable Formal Verification Solutions

By Malay Ganai , Aarti Gupta

  • eBook Price: $159.00
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  • ISBN13: 978-0-3876-9166-4
  • 360 Pages
  • User Level: Professionals
  • Publication Date: May 26, 2007
  • Available eBook Formats: PDF
Full Description
Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol. The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.
Table of Contents

Table of Contents

  1. Design Verification Challenges.
  2. Background.
  3. Part I: Basic Infrastructure.
  4. Efficient Boolean Representation.
  5. Hybrid DPLL
  6. Style SAT Solver.
  7. Part II: Falsification.
  8. SAT
  9. Based Bounded Model Checking.
  10. Distributed SAT
  11. Based BMC.
  12. Efficient Memory Modeling in BMC.
  13. BMC for Multi
  14. Clock Systems.
  15. Part III: Proof Methods.
  16. Proof by Induction.
  17. Unbounded Model Checking.
  18. Part IV: Abstraction/Refinement.
  19. Proof
  20. Based Iterative Abstraction.
  21. Part V: Verification Procedure.
  22. SAT
  23. Based Verification Framework.
  24. Synthesis for Verification.

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