Low Power Networks-on-Chip

By Cristina Silvano , Marcello Lajolo , Gianluca Palermo

Low Power Networks-on-Chip Cover Image

With power consumption now a key design constraint, recent years have seen growing research interest in these networks as an architectural solution for high-speed data transfer. This single-source reference covers some of the most important design techniques.

Full Description

  • ISBN13: 978-1-4419-6910-1
  • 310 Pages
  • Publication Date: October 6, 2010
  • Available eBook Formats: PDF
  • eBook Price: $129.00
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Full Description
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
Table of Contents

Table of Contents

  1. Network
  2. on
  3. Chip Power Estimation.
  4. Timing.
  5. synchronous/asynchronous communication.
  6. Network
  7. on
  8. Chip link design.
  9. Topology exploration.
  10. Network
  11. on
  12. Chip support for CMP/MPSoCs.
  13. Network design for 3D stacked logic and memory.
  14. Beyond the wired Network
  15. on
  16. Chip.
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