- Full Description
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
- Table of Contents
Table of Contents
- Chip Power Estimation.
- synchronous/asynchronous communication.
- Chip link design.
- Topology exploration.
- Chip support for CMP/MPSoCs.
- Network design for 3D stacked logic and memory.
- Beyond the wired Network
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