Integrated Circuits and Systems

Design for Manufacturability and Yield for Nano-Scale CMOS

Authors: Chiang, Charles, Kawa, Jamil

  • Addressing a new topic (DFM/DFY) critical at 90 nm and beyond
  • No book available today with comprehensive coverage of this topic
  • Book covers all CAD/CAE aspects of a SOC design flow
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eBook $139.00
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  • ISBN 978-1-4020-5188-3
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  • Download immediately after purchase
Hardcover $179.00
price for USA
  • ISBN 978-1-4020-5187-6
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  • This title is currently reprinting. You can pre-order your copy now.
Softcover $179.00
price for USA
  • ISBN 978-90-481-7303-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody’s responsibility.

Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design’s manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.

About the authors

Dr. Charles Chiang is R&D Director of the Advanced Technology Group at Synopsys Inc. in Mountain View, CA, USA

Table of contents (8 chapters)

  • Introduction

    Chiang, Charles C. (et al.)

    Pages 1-19

  • Random Defects

    Chiang, Charles C. (et al.)

    Pages 21-51

  • Systematic Yield - Lithography

    Chiang, Charles C. (et al.)

    Pages 53-97

  • Systematic Yield - Chemical Mechanical Polishing (CMP)

    Chiang, Charles C. (et al.)

    Pages 99-150

  • Variability & Parametric Yield

    Chiang, Charles C. (et al.)

    Pages 151-168

Buy this book

eBook $139.00
price for USA
  • ISBN 978-1-4020-5188-3
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Download immediately after purchase
Hardcover $179.00
price for USA
  • ISBN 978-1-4020-5187-6
  • Free shipping for individuals worldwide
  • This title is currently reprinting. You can pre-order your copy now.
Softcover $179.00
price for USA
  • ISBN 978-90-481-7303-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.

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Bibliographic Information

Bibliographic Information
Book Title
Design for Manufacturability and Yield for Nano-Scale CMOS
Authors
Series Title
Integrated Circuits and Systems
Copyright
2007
Publisher
Springer Netherlands
Copyright Holder
Springer Science+Business Media B.V.
eBook ISBN
978-1-4020-5188-3
DOI
10.1007/978-1-4020-5188-3
Hardcover ISBN
978-1-4020-5187-6
Softcover ISBN
978-90-481-7303-7
Series ISSN
1558-9412
Edition Number
1
Number of Pages
XXVII, 255
Topics