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Digital System Test and Testable Design

Using HDL Models and Architectures

Authors: Navabi, Zainalabedin

  • Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate
  • Simulations of gate models allows fault simulation and test generation, while Verilog test benches inject faults, evaluate fault coverage and apply new test patterns
  • Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods
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  • ISBN 978-1-4419-7547-8
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About this Textbook

Digital System Test and Testable Design: Using HDL Models and Architectures by: Zainalabedin Navabi This book is about digital system test and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware / software environment facilitates description of complex test programs and test strategies. •Combines design and test •Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate •Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns •Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods •Virtual testers (Verilog testbenches) play the role of ATEs for driving scan tests and examining the circuit under test •Verilog descriptions of scan designs and BIST architectures are available that can be used in actual designs •PLI test utilities developed in-text are available for download •Introductory Video for Verilog basics, software developed in-text, and PLI basics available for download •Powerpoint slides available for each chapter

About the authors

About the Author Dr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi’s involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1990. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of Arizona in 1978 and 1891, and his B.S. from the University of Texas at Austin in 1975. He is a senior member of IEEE, a member of IEEE Computer Society, member of ASEE, and ACM.

Table of contents (11 chapters)

  • Basics of Test and Role of HDLs

    Navabi, Zainalabedin

    Pages 1-20

  • Verilog HDL for Design and Test

    Navabi, Zainalabedin

    Pages 21-62

  • Fault and Defect Modeling

    Navabi, Zainalabedin

    Pages 63-101

  • Fault Simulation Applications and Methods

    Navabi, Zainalabedin

    Pages 103-142

  • Test Pattern Generation Methods and Algorithms

    Navabi, Zainalabedin

    Pages 143-174

Buy this book

eBook $69.99
price for USA
  • ISBN 978-1-4419-7548-5
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Download immediately after purchase
Hardcover $99.00
price for USA
  • ISBN 978-1-4419-7547-8
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Rent the ebook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
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Bibliographic Information

Bibliographic Information
Book Title
Digital System Test and Testable Design
Book Subtitle
Using HDL Models and Architectures
Authors
Copyright
2011
Publisher
Springer US
Copyright Holder
Springer Science+Business Media, LLC
eBook ISBN
978-1-4419-7548-5
DOI
10.1007/978-1-4419-7548-5
Hardcover ISBN
978-1-4419-7547-8
Edition Number
1
Number of Pages
XVII, 435
Topics