Theoretical Computer Science and General Issues

Power-Aware Computer Systems

4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers

Editors: Falsafi, Babak, Vijaykumar, T.N. (Eds.)

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About this book

Welcome to the proceedings of the Power-Aware Computer Systems (PACS 2004) workshop held in conjunction with the 37th Annual International Sym- sium on Microarchitecture (MICRO-37). The continued increase of power and energy dissipation in computer systems has resulted in higher cost, lower re- ability, and reduced battery life in portable systems. Consequently, power and energy have become ?rst-class constraints at all layers of modern computer s- tems. PACS 2004 is the fourth workshop in its series to explore techniques to reduce power and energy at all levels of computer systems and brings together academic and industry researchers. The papers in these proceedings span a wide spectrum of areas in pow- aware systems. We have grouped the papers into the following categories: (1) microarchitecture- and circuit-level techniques, (2) power-aware memory and interconnect systems, and (3) frequency- and voltage-scaling techniques. The ?rst paper in the microarchitecture group proposes banking and wri- back ?ltering to reduce register ?le power. The second paper in this group - timizes both delay and power of the issue queue by packing two instructions in each issue queue entry and by memorizing upper-order bits of the wake-up tag. The third paper proposes bit slicing the datapath to exploit narrow width operations, and the last paper proposes to migrate application threads from one core to another in a multi-core chip to address thermal problems.

Table of contents (13 chapters)

  • An Optimized Front-End Physical Register File with Banking and Writeback Filtering

    Pericàs, Miquel (et al.)

    Pages 1-14

  • Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization

    Sharkey, Joseph (et al.)

    Pages 15-29

  • Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors

    Kumar, Sumeet (et al.)

    Pages 30-45

  • Low-Overhead Core Swapping for Thermal Management

    Kursun, Eren (et al.)

    Pages 46-60

  • Software–Hardware Cooperative Power Management for Main Memory

    Huang, H. (et al.)

    Pages 61-77

Buy this book

eBook $69.99
price for USA
  • ISBN 978-3-540-31485-1
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Download immediately after purchase
Softcover $89.99
price for USA
  • ISBN 978-3-540-29790-1
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.

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Bibliographic Information

Bibliographic Information
Book Title
Power-Aware Computer Systems
Book Subtitle
4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers
Editors
  • Babak Falsafi
  • T.N. Vijaykumar
Series Title
Theoretical Computer Science and General Issues
Series Volume
3471
Copyright
2005
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer-Verlag Berlin Heidelberg
eBook ISBN
978-3-540-31485-1
DOI
10.1007/11574859
Softcover ISBN
978-3-540-29790-1
Edition Number
1
Number of Pages
X, 181
Topics